1. Field of the Invention
This invention relates to electrical connections in integrated semiconductor circuits. In particular, this invention relates to a dual damascene interconnect structure and to methods of making the interconnect structure.
2. Discussion of the Background
To form integrated circuits, discrete semiconductor devices must be wired together electrically. The electrical wiring used frequently includes damascene structures. Damascene structures are produced by forming grooves in an insulating layer and then filling the grooves with metal. Advances in damascene processing have led to processes characterized as dual damascene.
Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, via openings (i.e., contact holes) are also formed. In one dual damascene process, an insulating layer is coated with a photoresist, which is exposed through a first mask with image pattern of the via openings. The pattern is anisotropically etched in the upper half of the insulating layer. The photoresist is then exposed through a second mask with an image pattern of conductive line openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
A number of dual damascene processes have been developed, including processes using an insulating layer that includes an etch stop layer. In an example of such a process, a first layer of insulator is deposited over a first level of patterned metal to which electrical contacts are to be selectively established. The first layer is planarized, if the underlying structure is not formed using a damascene process, and then covered by an etch stop material. Contact holes are defined in the etch stop material by a first lithography at locations where vias are required. The first insulator layer is not etched at this time. A second insulator layer, having a thickness equal to the thickness of the second level of patterned metal of the multi-level structure being formed, is deposited over the etch stop material. The second insulator layer, in turn, is etched by a second photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed via holes in the etch stop material. In those locations where the via holes are exposed, the etching is continued into the first insulator layer to uncover the underlying first level of patterned metal. The horizontal channels and vertical holes etched into the second and first insulator layers are next overfilled with metal. As a final step, excess metal on top of the second insulator layer but not in the channels or holes is removed by etching or chemical-mechanical polishing.
In another example of a dual damascene process using an etch stop layer, a first layer of insulator is deposited over a first level of patterned metal to which electrical contacts are to be selectively formed. The first layer is planarized, if the prior structure is not formed using a damascene process, and then covered by an etch stop material. A second insulator layer, having a thickness equal to the thickness of the second level of patterned metal of the multi-level structure being formed, is deposited over the etch stop material. Contact holes are then defined on top of the second insulator layer by a first lithography at locations where vias are to be formed. The second insulator layer, the etch stop layer and the first insulator layer are etched at this time to form the via holes. A second photolithography is performed on the second insulator material to define desired wiring channels, some of which will be in alignment with the previously formed via holes. A second plasma etch process, requiring an etch selectivity between the second insulator material and the etch stop material, is used to form horizontal channels in the second insulator layer. The horizontal channels and the vertical via holes are next overfilled with metal. As a final step, excess metal on top of the second insulator layer but not in the channels or holes is removed by etching or chemical-mechanical polishing.
In still another example of a dual damascene process using an etch stop layer, a first layer of insulator is deposited over a first level of patterned metal to which electrical contacts are to be selectively formed. The first layer is planarized, if the underlying structure is not formed using a damascene process, and then covered by an etch stop material. A second insulator layer, having a thickness equal to the thickness of the second level of patterned metal of the multi-level structure being formed, is deposited over the etch stop material. Horizontal channels are then defined on top of the second insulator layer by a first lithography at locations where metal conducting trenches are required. The second insulator layer is etched at this time, either selectively stopping at the etch stop layer or being timely controlled to reach the required trench depth. A second photolithography is performed on the second insulator material to define via openings, some of which will be in alignment with the previously formed channels. A second plasma etch process is performed to open the via holes. The horizontal channels in the second insulator layer and the vertical via holes are next overfilled with metal. As a final step, excess metal on top of the second insulator layer but not in the channels or holes is removed by etching or chemical-mechanical polishing. In conventional dual damascene processes, the etch stop layer used is typically silicon nitride.
Huang et al. U.S. Pat. No. 5,635,423 reports a modified dual damascene process in which an initial opening in a trench dielectric is enlarged while simultaneously extending a via opening through an etch stop layer and a via dielectric.
Avanzino et al. U.S. Pat. No. 5,795,823 reports the fabrication of conductive lines and connecting vias using dual damascene with only one mask pattern. This is also reported by Avanzino et al. in U.S. Pat. No. 5,614,765.
Yen U.S. Pat. No. 5,861,676, reports a method of forming interconnects and contacts between elements in a semiconductor or integrated circuit.
Dai et al U.S. Pat. No. 5,877,075 reports forming dual damascene patterns using a single photoresist process.
Dai U.S. Pat. No. 5,877,076 reports a dual damascene process using opposite type two-layered photoresist.
Dai U.S. Pat. No. 5,882,996 discloses a method for patterning dual damascene interconnections using a developer soluble ARC interstitial layer.
In spite of known techniques for forming contacts and interconnects, increases in device density and demands for increased processing efficiency have spurred new efforts to effectively produce semiconductor interconnections.